Guides
Designing with agentee
One guide per stage of a design, in the order you meet them. Each one is written for the person directing the agent and for the agent itself: every command is real and every key is in the reference.
Start here
Your first board
From an empty directory to a checked, routed two layer board and a fab package: board spec, KiCad parts, a schematic, placement, routing and Gerbers.
Set up your coding agent
Install the agentee skill, add the MCP server to Claude Code, Codex, Cursor or any MCP client, and give the agent a brief it can work from.
Coming from KiCad
What agentee takes from KiCad and what it does differently: the libraries it imports from, importing a whole board, and how the concepts map.
Design
Board specs, stackups and net classes
Pick a fab and a real stackup, define a net class per kind of net, and put impedance and current targets on them so check solves the widths.
Parts: import or draw
Search and import KiCad symbols and footprints, fix what the fab rejects, and build a part from its datasheet when KiCad does not have it.
Writing schematics
Parts, nets and classes with agentee edit, batches of commands, sheets for large designs, and the signal level check that catches dividers between VIL and VIH.
Placement, routing and pours
Automatic placement, ground and supply pours, plane ties, the autorouter, silk labels, test pads and the design rule checks that gate the fab package.
Controlled impedance and pairs
Closed form and GPU field solved trace widths, coplanar RF lines, differential pairs, length matching and interfaces like USB 3.
HDI: microvias and lamination
Blind, buried and microvias, stacked and skip vias, via-in-pad, backdrills and controlled depth drilling, and how the lamination decides what can be drilled.
Simulate
RF simulation: FDTD and cascade
Run a full-wave FDTD of a layout on the GPU, drop vendor S-parameters and noise data into it, and read gain, noise figure, match and stability.
Eye diagrams, PDN and S-parameters
Push a bit stream through a channel and read the eye, check a power rail’s impedance against a target, and run TDR, mixed-mode and crosstalk analysis.
DC drop and thermal
Solve every copper layer for voltage drop and current density, then the board’s temperature with each part’s power, in seconds.
Logic simulation
Simulate the digital parts of a schematic straight from its netlist: 74 series models, stimulus, assertions, setup and hold checks, and a VCD out.
Ship
Fab package, BOM and pricing
Write Gerbers, drills, BOM and placement for JLCPCB or any fab, price the BOM at Mouser and Farnell, and export a STEP for the enclosure.
The viewer
A live window that reloads on every save, where a person can watch the agent work, move parts, route tracks and place vias by hand.
Checking designs in CI
Run agentee check on every push, fail the build on errors, keep simulation results fresh, and attach a fab package to a release.