Reference
File format reference
Every key of every file, split by topic. It is the same text agentee docs prints and the MCP server returns as format_reference, so an agent offline reads exactly this.
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Project files
A project is a directory of TOML files loaded by their suffix: boards, symbols, footprints, schematics, layouts and simulations.
Editing with agentee edit
The commands that write every key of a schematic, layout or board spec, keep the file’s comments, and check what they changed.
Units and coordinates
Millimetres by default, unit strings for everything else, Y growing down and rotation counter-clockwise on screen.
Workflow
The order a design is built in, from importing parts to writing the fab package.
Board
Board spec
The *.board.toml file: fab preset, outline and cutouts, stackup, via types and net classes with impedance and current targets.
Stackup presets
Every JLCPCB impedance build, the PCBWay standard builds and two generic HDI stackups, named by the fab’s own code.
Lamination
The build-up sequence of presses and drill steps, derived from the stackup or listed by hand, that decides which vias can be drilled.
Via types
Through, blind, buried and microvias, stacked and skip vias, controlled depth drilling, backdrills and IPC-4761 via fill.
Fab rules
Every fab rule key, and the values of the generic, jlcpcb and hdi presets with the line of the fab’s capability page each one comes from.
Design rule checks
Every layout rule with its id, severity and the condition it runs under: copper, drills, mask, silk, assembly, zones, signals, test access and placement.
Impedance and loss
Trace geometry per class and layer, closed form and field solved impedance, differential pairs, and the loss model with roughness and ENIG.
Parts
Symbols
The *.sym.toml file: pins, graphics, generated box bodies, multi-unit symbols and logic levels for the signal check.
Footprints
The *.fp.toml file: pad rows, pad shapes and layers, edge pads, zone connections, courtyards, silk and 3D models.
Graphics
The shapes symbols, footprints and layouts share: lines, rectangles, polylines, polygons, circles, arcs and text.
Schematic and layout
Schematics
The *.sch.toml file: placed parts, nets as lists of pins, net classes, rails and the signal level check, and sheets for large designs.
Layouts
The *.pcb.toml file: placements, tracks, vias, fanouts, stitching, zones, cutouts, silk, artwork, test access and the version watermark.
Automatic placement
agentee place: connectors on edges, large chips central, decoupling caps at their pins, then legalised and refined.
Autorouting
agentee route, tie, tune and neck: grid routing that keeps class widths, clearances and vias, plane ties, length matching and neck-downs.
Interfaces
What a link must meet, from USB 3 to a 50 ohm RF line: impedance, skew, length, vias, stubs, reference planes and return vias.
Editing in the viewer
Moving parts, routing tracks and placing vias by hand in agentee view, saved back into the same TOML.
Simulation
FDTD simulation
A full-wave FDTD run of a layout on the GPU with lumped ports on pads, giving S-parameters as JSON and Touchstone.
Channel and eye
A bit stream through an S-parameter path with CTLE, DFE and IBIS drivers and receivers, read as an eye.
Power distribution network
The impedance of a power rail from its sinks, decaps and VRM against a target, with the anti-resonances to fix.
Analysing S-parameters
TDR, mixed-mode pairs, crosstalk, passivity and reciprocity from any FDTD or cascade result.
Losses in the FDTD
Causal dielectric loss, surface impedance with skin effect, roughness and ENIG nickel, and the edge corrections of the mesh.
Field maps and emissions
E and H field maps in the first prepreg and the far field, with radiated power and the field at 3 m against FCC class B.
Cascade
Vendor S-parameters, noise and linearity dropped into a board sim: gain, noise figure, IIP3, P1dB, SFDR and stability.
DC drop
Every copper layer solved as a resistive sheet: drop, current density, load voltages and the busiest vias.
Thermal
Steady state conduction through FR4, copper and vias with convection from both faces, solved on the GPU.
Logic simulation
An event-driven sim of a schematic’s digital parts: 74 series models, primitives, stimulus, assertions, setup and hold, VCD out.
Output
Importing a KiCad board
agentee import board turns a .kicad_pcb into a board spec, layout, netlist schematic, footprints and symbols.
Fab package
The Gerbers, drill files, BOM, placement, IPC-D-356 netlist, test points and fab notes agentee fab writes.
Distributors and pricing
agentee parts: BOM pricing at Mouser and Farnell and cheaper parts that drop in without a downgrade.