# agentee

> Electronics design for coding agents. A design is a directory of plain TOML files (board spec, symbols, footprints, schematics, layouts and simulations) that an agent writes and edits. The `agentee` CLI checks them against the fab, renders them to PNG, solves trace impedance, runs FDTD, cascade, channel, PDN, DC drop, thermal and logic simulations on the GPU, and writes the fab package. A person watches in a live viewer and can edit the layout by hand.

Give an agent the skill first: it teaches the edit, check, render loop, the order to build a design in, and how to iterate on simulations without burning GPU hours. `agentee docs` prints the full file format reference offline, and `agentee mcp <project>` serves the same operations over MCP.

```sh
curl -fsSL https://agentee.sh/install.sh | sh        # Linux and macOS
irm https://agentee.sh/install.ps1 | iex             # Windows PowerShell
cargo install --git https://github.com/v0l/agentee agentee   # from source
npx skills add https://agentee.sh                     # the agent skill
```

## Start

- [Agent skill](https://agentee.sh/.well-known/agent-skills/agentee/SKILL.md): Design and iterate on electronics with agentee, where boards, symbols, footprints, schematics, layouts and simulations are plain TOML files checked by the `agentee` CLI or MCP server. Use when creating or editing a design with `agentee edit` (sch, pcb, board commands), or when hand-writing `*.board.toml`, `*.sym.toml`, `*.fp.toml`, `*.sch.toml`, `*.pcb.toml` or `*.sim.toml` files, importing KiCad parts, fixing `agentee check` errors, routing a layout, sizing traces for impedance or current, running FDTD, cascade, channel, PDN, DC drop or thermal sims, or writing a fab package.
- [Download](https://agentee.sh/download/index.html.md): install on Linux, macOS and Windows, or build from source
- [Your first board](https://agentee.sh/guides/getting-started/index.html.md): From an empty directory to a checked, routed two layer board and a fab package: board spec, KiCad parts, a schematic, placement, routing and Gerbers.
- [Set up your coding agent](https://agentee.sh/guides/agents/index.html.md): Install the agentee skill, add the MCP server to Claude Code, Codex, Cursor or any MCP client, and give the agent a brief it can work from.
- [Coming from KiCad](https://agentee.sh/guides/kicad/index.html.md): What agentee takes from KiCad and what it does differently: the libraries it imports from, importing a whole board, and how the concepts map.

## Guides

- [Board specs, stackups and net classes](https://agentee.sh/guides/board-spec/index.html.md): Pick a fab and a real stackup, define a net class per kind of net, and put impedance and current targets on them so check solves the widths.
- [Parts: import or draw](https://agentee.sh/guides/parts/index.html.md): Search and import KiCad symbols and footprints, fix what the fab rejects, and build a part from its datasheet when KiCad does not have it.
- [Writing schematics](https://agentee.sh/guides/schematics/index.html.md): Parts, nets and classes with agentee edit, batches of commands, sheets for large designs, and the signal level check that catches dividers between VIL and VIH.
- [Placement, routing and pours](https://agentee.sh/guides/layout/index.html.md): Automatic placement, ground and supply pours, plane ties, the autorouter, silk labels, test pads and the design rule checks that gate the fab package.
- [Controlled impedance and pairs](https://agentee.sh/guides/impedance/index.html.md): Closed form and GPU field solved trace widths, coplanar RF lines, differential pairs, length matching and interfaces like USB 3.
- [HDI: microvias and lamination](https://agentee.sh/guides/hdi/index.html.md): Blind, buried and microvias, stacked and skip vias, via-in-pad, backdrills and controlled depth drilling, and how the lamination decides what can be drilled.
- [RF simulation: FDTD and cascade](https://agentee.sh/guides/rf-simulation/index.html.md): Run a full-wave FDTD of a layout on the GPU, drop vendor S-parameters and noise data into it, and read gain, noise figure, match and stability.
- [Eye diagrams, PDN and S-parameters](https://agentee.sh/guides/signal-integrity/index.html.md): Push a bit stream through a channel and read the eye, check a power rail’s impedance against a target, and run TDR, mixed-mode and crosstalk analysis.
- [DC drop and thermal](https://agentee.sh/guides/power-and-thermal/index.html.md): Solve every copper layer for voltage drop and current density, then the board’s temperature with each part’s power, in seconds.
- [Logic simulation](https://agentee.sh/guides/logic-simulation/index.html.md): Simulate the digital parts of a schematic straight from its netlist: 74 series models, stimulus, assertions, setup and hold checks, and a VCD out.
- [Fab package, BOM and pricing](https://agentee.sh/guides/fab/index.html.md): Write Gerbers, drills, BOM and placement for JLCPCB or any fab, price the BOM at Mouser and Farnell, and export a STEP for the enclosure.
- [The viewer](https://agentee.sh/guides/viewer/index.html.md): A live window that reloads on every save, where a person can watch the agent work, move parts, route tracks and place vias by hand.
- [Checking designs in CI](https://agentee.sh/guides/ci/index.html.md): Run agentee check on every push, fail the build on errors, keep simulation results fresh, and attach a fab package to a release.

## Reference

- [Project files](https://agentee.sh/reference/overview/index.html.md): A project is a directory of TOML files loaded by their suffix: boards, symbols, footprints, schematics, layouts and simulations.
- [Editing with agentee edit](https://agentee.sh/reference/edit/index.html.md): The commands that write every key of a schematic, layout or board spec, keep the file’s comments, and check what they changed.
- [Units and coordinates](https://agentee.sh/reference/units/index.html.md): Millimetres by default, unit strings for everything else, Y growing down and rotation counter-clockwise on screen.
- [Workflow](https://agentee.sh/reference/workflow/index.html.md): The order a design is built in, from importing parts to writing the fab package.
- [Board spec](https://agentee.sh/reference/board/index.html.md): The *.board.toml file: fab preset, outline and cutouts, stackup, via types and net classes with impedance and current targets.
- [Stackup presets](https://agentee.sh/reference/stackups/index.html.md): Every JLCPCB impedance build, the PCBWay standard builds and two generic HDI stackups, named by the fab’s own code.
- [Lamination](https://agentee.sh/reference/lamination/index.html.md): The build-up sequence of presses and drill steps, derived from the stackup or listed by hand, that decides which vias can be drilled.
- [Via types](https://agentee.sh/reference/vias/index.html.md): Through, blind, buried and microvias, stacked and skip vias, controlled depth drilling, backdrills and IPC-4761 via fill.
- [Fab rules](https://agentee.sh/reference/rules/index.html.md): Every fab rule key, and the values of the generic, jlcpcb and hdi presets with the line of the fab’s capability page each one comes from.
- [Design rule checks](https://agentee.sh/reference/drc/index.html.md): Every layout rule with its id, severity and the condition it runs under: copper, drills, mask, silk, assembly, zones, signals, test access and placement.
- [Impedance and loss](https://agentee.sh/reference/impedance/index.html.md): Trace geometry per class and layer, closed form and field solved impedance, differential pairs, and the loss model with roughness and ENIG.
- [Symbols](https://agentee.sh/reference/symbol/index.html.md): The *.sym.toml file: pins, graphics, generated box bodies, multi-unit symbols and logic levels for the signal check.
- [Footprints](https://agentee.sh/reference/footprint/index.html.md): The *.fp.toml file: pad rows, pad shapes and layers, edge pads, zone connections, courtyards, silk and 3D models.
- [Graphics](https://agentee.sh/reference/graphics/index.html.md): The shapes symbols, footprints and layouts share: lines, rectangles, polylines, polygons, circles, arcs and text.
- [Schematics](https://agentee.sh/reference/schematic/index.html.md): The *.sch.toml file: placed parts, nets as lists of pins, net classes, rails and the signal level check, and sheets for large designs.
- [Layouts](https://agentee.sh/reference/layout/index.html.md): The *.pcb.toml file: placements, tracks, vias, fanouts, stitching, zones, cutouts, silk, artwork, test access and the version watermark.
- [Automatic placement](https://agentee.sh/reference/placement/index.html.md): agentee place: connectors on edges, large chips central, decoupling caps at their pins, then legalised and refined.
- [Autorouting](https://agentee.sh/reference/routing/index.html.md): agentee route, tie, tune and neck: grid routing that keeps class widths, clearances and vias, plane ties, length matching and neck-downs.
- [Interfaces](https://agentee.sh/reference/interfaces/index.html.md): What a link must meet, from USB 3 to a 50 ohm RF line: impedance, skew, length, vias, stubs, reference planes and return vias.
- [Editing in the viewer](https://agentee.sh/reference/viewer/index.html.md): Moving parts, routing tracks and placing vias by hand in agentee view, saved back into the same TOML.
- [FDTD simulation](https://agentee.sh/reference/fdtd/index.html.md): A full-wave FDTD run of a layout on the GPU with lumped ports on pads, giving S-parameters as JSON and Touchstone.
- [Channel and eye](https://agentee.sh/reference/channel/index.html.md): A bit stream through an S-parameter path with CTLE, DFE and IBIS drivers and receivers, read as an eye.
- [Power distribution network](https://agentee.sh/reference/pdn/index.html.md): The impedance of a power rail from its sinks, decaps and VRM against a target, with the anti-resonances to fix.
- [Analysing S-parameters](https://agentee.sh/reference/sparam/index.html.md): TDR, mixed-mode pairs, crosstalk, passivity and reciprocity from any FDTD or cascade result.
- [Losses in the FDTD](https://agentee.sh/reference/fdtd-losses/index.html.md): Causal dielectric loss, surface impedance with skin effect, roughness and ENIG nickel, and the edge corrections of the mesh.
- [Field maps and emissions](https://agentee.sh/reference/fields/index.html.md): E and H field maps in the first prepreg and the far field, with radiated power and the field at 3 m against FCC class B.
- [Cascade](https://agentee.sh/reference/cascade/index.html.md): Vendor S-parameters, noise and linearity dropped into a board sim: gain, noise figure, IIP3, P1dB, SFDR and stability.
- [DC drop](https://agentee.sh/reference/dc/index.html.md): Every copper layer solved as a resistive sheet: drop, current density, load voltages and the busiest vias.
- [Thermal](https://agentee.sh/reference/thermal/index.html.md): Steady state conduction through FR4, copper and vias with convection from both faces, solved on the GPU.
- [Logic simulation](https://agentee.sh/reference/logic/index.html.md): An event-driven sim of a schematic’s digital parts: 74 series models, primitives, stimulus, assertions, setup and hold, VCD out.
- [Importing a KiCad board](https://agentee.sh/reference/kicad-import/index.html.md): agentee import board turns a .kicad_pcb into a board spec, layout, netlist schematic, footprints and symbols.
- [Fab package](https://agentee.sh/reference/fab/index.html.md): The Gerbers, drill files, BOM, placement, IPC-D-356 netlist, test points and fab notes agentee fab writes.
- [Distributors and pricing](https://agentee.sh/reference/distributors/index.html.md): agentee parts: BOM pricing at Mouser and Farnell and cheaper parts that drop in without a downgrade.

## Tools

- [Command line](https://agentee.sh/cli/index.html.md): every command and flag as the binary prints it
- [MCP server](https://agentee.sh/mcp/index.html.md): 30 tools and client setup

## Optional

- [A bias-tee powered LNA](https://agentee.sh/examples/lna/index.html.md): A wideband SPF5189Z low noise amplifier for an SDR, from schematic to a routed four layer layout, with FDTD, a cascade with vendor data, DC drop and thermal sims.
- [Great Scott Gadgets’ HackRF Pro, imported from KiCad](https://agentee.sh/examples/hackrf-pro/index.html.md): The Praline board of the HackRF Pro, imported whole from its KiCad files: a large real layout to check, render and benchmark against.
- [Logic simulations of a counter and an I2C bus](https://agentee.sh/examples/logic/index.html.md): Two schematics simulated straight from their netlists: a 74HC161 counting into a 74HC138, and an open-drain I2C bus captured by a 74HC595.
- [Everything in one file](https://agentee.sh/llms-full.txt): the guides, the full reference, the CLI and MCP tool reference and the skill
- [Source](https://github.com/v0l/agentee): GPL-3.0-or-later